(A) Field of the Invention
The present invention relates to a semiconductor device and its manufacture method, and more particularly to a semiconductor device manufacture method capable of preventing a lower manufacture yield when wiring and pads are formed by a damascene method and to a semiconductor device having a structure suitable for the manufacture method.
(B) Description of the Related Art
Design rules of multi-layer wiring structures are becoming smaller as the degree of integration and micro patterning of semiconductor integrated circuit devices (LSI) becomes higher. A method of forming wiring by partially etching a metal layer is nowadays associated with some technical limit. In order to solve this problem, a damascene method is utilized by which a groove for wiring or a via hole for conductive plug is formed through an insulating film, and thereafter conductive material is filled in this groove or via hole.
On a multi layer wiring structure formed through micro patterning, pads are finally formed for connection to external circuits and for inspection. This pad has a relatively large size as compared to other patterns in the multi layer wiring structure.
With reference to FIG. 9A, a conventional method of forming a pad by using a damascene method will be described.
FIG. 9A is a cross-sectional view of a pad formed by a damascene method. First, on the surface of an interlayer insulating film 500 formed on a silicon substrate, an etching stopper film 501 and an insulating film 502 are deposited. An opening 503 is formed through these two layers.
Next, a barrier metal layer 504 is formed covering the inner surface of the opening 503 and the upper surface of the insulating film 502. A copper layer is formed on the surface of the barrier metal layer 504 by sputtering. By using this copper layer as a seed layer, a thick copper layer is formed by plating. The copper layer formed by plating is filled in the opening 503.
The copper layer and barrier metal layer deposited on the insulating film 502 are removed by chemical mechanical polishing (CMP). As shown in FIG. 9A, a pad 505 made of the copper layer formed by plating is left in the opening 503.
If the area of the pad 505 is large, the upper surface of the pad 505 becomes depressed. This phenomenon is called dishing. The upper surface of the insulating film 502 gradually lowers toward the pad 505. This phenomenon is called erosion. The pad after CMP has a depressed surface.
As shown in FIG. 9B, on the surface with dishing and erosion, an etching stopper film 506 of silicon nitride and an interlayer insulating film 507 of silicon oxide are deposited. The surface of the interlayer insulating film 506 has a depressed surface in conformity with the surface of the underlying layer. A resist film is formed on the surface of the interlayer insulating film 507. When a pattern is formed by photolithography, a focus depth margin during exposure becomes small. If wiring is formed on this depressed surface by a damascene method, residue of a conductive film is formed after CMP and plugs may be electrically shorted.
FIG. 9C is a cross-sectional view of a pad in which the insulating film 502 shown in FIG. 9A is replaced with a two-layer structure of a lower insulating film 502A and an upper insulating film 502B. The lower insulating film 502A is made of silicon oxide doped with fluorine, and the upper insulating film 502B is made of silicon oxide. As erosion is formed, the lower insulating film 502A is exposed in some cases at the area contacting the border of the opening 503. Silicon oxide doped with fluorine has a high hygroscopicity so that the exposed insulating film 502A absorbs moisture. The silicon oxide film doped with fluorine and absorbed moisture may generate gas at a succeeding heat treatment process or may cause a lower tight adhesion.
If the lower insulating film is made of insulating organic material such as polyallyl ether, in addition to moisture absorption and lowered tight adhesion, the following problem arises. As shown in FIG. 9D, before wiring is formed on the pad 505 by a damascene method, an etching stopper film 506 of silicon nitride is formed. When this etching stopper film 506 is formed by plasma enhanced chemical vapor deposition (PE-CVD), plasma of H2 and NH3 is generated. Therefore, the exposed insulating film 502A is exposed by plasma of H2 and NH3 and etched by the plasma and a gap is formed in some cases. The film itself may be decomposed and the tight adhesion may be lowered.
In order to remove a thin copper oxide film formed on the surface of the Cu pad before the etching stopper film 506 is formed, a reduction process is performed by using, for example, NH3 plasma. During this reduction process, the insulating film 502A may be decomposed.
FIGS. 10A to 10C are plan views of pads proposed to suppress the generation of dishing and erosion. The pads shown in FIGS. 10A and 10C are disclosed in JP-A-11-150114, and the pad shown in FIG. 10B is disclosed in JP-A-10-229085. In either case, insulating regions 502a of the insulating layer 502 shown in FIG. 9A are left. These insulating regions 502a function as a polishing stopper layer for CMP so that generation of dishing and erosion can be suppressed.
FIG. 11 is a plan view of a pad and a wiring pattern continuous with the pad. The wiring pattern 510 is connected to one side of a square pad 505. A plurality of square insulating regions 502a are disposed in the pad 505 in a matrix shape. In order to improve the effects of suppressing the generation of dishing and erosion, the size of each insulating region 502a is made smaller and the number of regions is increased, as compared to the regions shown in FIG. 10C.
The width of the wiring pattern 510 is represented by W1, the distance from the outer periphery of the pad 505 to the outermost insulating region 502a is represented by W2, and a distance between adjacent insulating regions 502a is represented by W3. Consider a closed line 511 which traverses the wiring pattern 510 and extends along a plurality of insulating regions 502a disposed nearest to the border line between the pad 505 and wiring pattern 510. In the pad shown in FIG. 11, the closed line 511 extends along the insides of the six insulating regions 502a. In the following, it is assumed that the closed line 511 extends along (n+1) insulating regions.
When current flows from the wiring 510 to the pad 505, current inflowing to the closed line 511 is equal to current outflowing from the closed line 511. Namely, the current passing through the length W1 where the closed line 511 and wiring 510 are crossed is equal to the current passing through the length of 2×W2+n×W3 where the closed line 511 and wiring 510 cross.
If the following inequality is satisfied and the density of current flowing in the wiring 510 takes an allowable limit value, the density of current flowing along a direction crossing the closed line 511 exceeds an allowable limit value:W1>2×W2+n×W3
The characteristics of a semiconductor device formed on a silicon substrate are inspected, for example, by contacting a conductive probe to the pad 505. If the insulating regions 502a are dispersed in the inside of the pad 505, contact between the pad 505 and conductive probe may become unstable.